Intel, AMD Competition in Data Center Heating Up Again

NEW-PRODUCT LAUNCH: AMD is unveiling the next generation of its Xen core architecture and GPU accelerators, while Intel is readying a 48-core Xeon server chip.

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SAN FRANCISCO—The competition between Intel and Advanced Micro Devices in the massive space for data center processors is lining up to be the fiercest since 2003, when AMD launched the first Opteron processor that helped it grab more than 20 percent of the market from its larger rival before ceding its gains over the following years.

AMD President and CEO Lisa Su and other executives three years ago announced their intention to make chip vendor once again relevant in the data center with the new Zen core architecture that is the foundation of the company’s Epyc server chips, which were introduced last year. At an event here Nov. 6, the executives announced the next generation of the architecture—Zen 2—aggressively stating that the data center is key to AMD’s future and that they didn’t intend to be merely a complement to Intel.

“We’re not talking about being a niche player,” Su told journalists and analysts. “We’re not talking second-source.”

AMD Doesn't Want to Take a Back Seat Anymore

AMD, she said, intends to take center stage with other major players in the industry.

The company’s event—which also included the introduction of the next-generation of its Radeon Instinct GPU accelerators and the announcement that public cloud leader Amazon Web Services (AWS) is offering instances powered by the Epyc chips—came two days after Intel officials unveiled a Xeon “Cascade Lake” series of chips with up to 48 cores and representing the company’s fastest server processors yet.

Intel for years has owned more than 95 percent a data center chip market that AMD officials said is about $20 billion today and will grow to $29 billion by 2021. However, with the rapid changes in the data center driven by such factors as the rise of the cloud, the proliferation of mobile devices, the expansion of compute to the network edge and the internet of things (IoT), other chip players—including IBM and Arm—have seen an opportunity to grab some of Intel’s market share.

Intel also has shown some vulnerability in recent years, with struggles to come out with a 10-nanometer chip—the first such processor isn’t due until 2020—and instability in its executive lineup with the abrupt resignation earlier this year of CEO Brian Krzanich. At the same time, the company has to compete with a stronger Taiwan Semiconductor Manufacturing Corp. (TSMC) in manufacturing.

“It’s very much like the two companies have switched places,” Rob Enderle, principal analyst with The Enderle Group, told eWEEK, noting AMD’s troubles in the past to fulfill promises.

AMD Lays Out Zens 2 Design

At the event, AMD officials laid out the Zen 2 architecture and the first of the 7nm Epyc chips, codenamed Rome, which is sampling now and due out in 2019. The Zen 2 processors will have multiple dies in a single socket, rather than having a single monolithic die. It also introduces the concept of what Su called “chiplets” —7nm silicon housed in a 14nm I/O die—that will drive compute power as well as fast connectivity.

Similarly, Intel’s upcoming 48-core, 14nm processors, manufactured by TSMC, also are designed with multiple dies on a single package. Company officials said the chips were aimed at such workloads as high-performance computing (HPC), artificial intelligence (AI) and infrastructure-as-a-service (IaaS), similar to those that AMD executives said were key use cases for the Epyc chips.

The Intel chips, which also include 12 DDR4 memory channels per socket, will be a topic of discussion by Intel at the upcoming SC18 supercomputing show, which starts the week of Nov. 12 in Dallas. They said the new chips offer 20 percent more performance than the current Xeon chips and up to 3.4 times more than the current Epyc chips in some workloads.

Multi-die designs like those in Epyc and the upcoming Xeon processors are important, given the new kinds of workloads coming into cloud and on-premises data centers and the challenges vendors face in driving performance gains as processors shrink, according to Patrick Moorhead, principal analyst with Moor Insights and Strategy.

Smaller Chips Being Produced Using Different Processes

“This is the direction the industry is going, as it moves away from running a lot of cores on big, monolithic dies,” Moorhead told eWEEK. “To keep innovation going, the industry is building smaller chips with different processes and different packaging to tie all of it together.”

The Rome chip will house up to 64 cores and 128 threads—the current “Naples” Epyc chips have 32 cores and 64 threads—and will support the PCIe 4.0 standard for fast interconnect, doubling the bandwidth per channel of the previous generation.

The Zen 2 architecture also includes an enhanced version of AMD’s Infinity Fabric to drive the modular design by linking the various pieces on the die. The new architecture will deliver twice the performance per socket than the Naples chip and four times the floating point performance per socket, Su said.

There also are such enhancements as improved branch predictor, better instruction pre-fetching, and security features like hardware-based Spectre mitigation and more flexibility in memory encryption. In addition, Rome not only will be backward-compatible with Naples but also forward-compatible with the upcoming Milan based on the Zen 3 architecture, which will follow Rome in 2020.

Along with Zen 2, AMD also introduced the Radeon Instinct MI60 and MI50 GPU accelerator, the follow-on to the MI25 accelerator announced last year. It’s built on a 7nm process and the company’s Vega architecture. Such accelerators have become key to data center environments both in HPC and the enterprise to accelerate highly parallel workloads like deep learning and rendering applications.

Higher Performance Benchmarks

The MI60 provides up to 7.4 TFLOPS of peak performance, while the MI50 delivers TFLOPS. David Wang, senior vice president of engineering in AMD’s Radeon Technology Group, will deliver 8.8 times the performance of the MI25 in some workloads and has twice the memory bandwidth.

The MI60 accelerator is due out this quarter.

At the same time, AMD also unveiled version 2.0 of the ROCm open-software platform for the new Instinct accelerators, enabling users to roll out high-performance and highly efficient systems in an open environment.

Moorhead said AMD’s Instinct GPUs will be key as the company competes with Nvidia, which leads the GPU accelerator market. AMD has always had good hardware but has fallen short in software. The ROCm software is helping the company to build up its software capabilities. In addition, MI60 is coming in at 7nm, while Nvidia is still at 16nm. However, Nvidia has a range of specialized cores—such as TensorCores—aimed at particular workloads, while it’s unclear if AMD will have a similar array, the analyst said.

After the Opteron launch, AMD lost market share when it failed to live up to performance and other promises. However, both Moorhead and Enderle said the company has met expectations with its first Zen-based Epyc chips. Enderle said the presentations by Su and other executives at the event here were more aggressive in their push backs against Intel, an indication of AMD’s growing confidence in its capabilities around innovation and product delivery.

The addition of AWS as a cloud partner is an important step as AMD continues to grow its ecosystem. Already providers like Microsoft Azure, Baidu and Tencent already have Epyc-based cloud instances, and Oracle officials last month said they would put the chips into bare-metals instances in the Oracle Cloud Infrastructure.